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Chapter 1 |
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1. |
Introduction |
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Chapter 2 |
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1. |
Basics of MOS Transistor: Introduction to MOSFET |
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2. |
Basics of MOS Transistor: Gate Voltage & Accumulation of Negative Charge |
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3. |
Basics of MOS Transistor: NChannel Formation Between Source & Drain |
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4. |
Basics of MOS Transistor: Impact Of Substrate Potential On threshold Voltage |
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5. |
Basics of MOS Transistor: Threshold voltage with body complete |
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6. |
Basics of MOS Transistor: Exercise 1 |
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7. |
Basics of MOS Transistor: Excercise 2 |
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Chapter 3 |
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1. |
SpecificationsToCHIP |
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2. |
Chip Dimension And Intro To Preplaced Cells |
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3. |
Pre Placed Cells Concluded |
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4. |
Decoupling Capacitors And Power Plan |
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5. |
Example For Netlist And Pin Placement |
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6. |
Pin Placement And Intro To PNR |
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7. |
Example Continued For PNR |
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8. |
Placement And Optimize Placement |
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9. |
Optimize Placement Continued |
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10. |
Optimize Placement Concluded |
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11. |
STA ideal clocks |
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12. |
STA ideal clocks with Setup Time. |
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13. |
STA ideal clocks with Example |
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14. |
STA ideal multiple clocks |
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15. |
STA ideal multiple clocks with example |
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16. |
STA Data slew check |
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17. |
STA Data slew check example |
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18. |
ClockTreeSyntehsis HTree |
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Chapter 4 |
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1. |
Introduction to Clock Tree |
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2. |
Skew Pulse Width Quality Checks |
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3. |
Duty Cycle Latency Quality Checks |
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4. |
Latenct Power Quality Check |
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5. |
Power Quality Check |
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6. |
Power Crosstalk Quality Check |
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7. |
Delta Delay Quality Check |
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8. |
Glitch Quality Check |
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Chapter 5 |
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1. |
HTree Skew Check |
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2. |
HTree Pulse Width Duty Cycle Check |
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3. |
Htree Latency Power Check |
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Chapter 6 |
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1. |
Clock tree Modelling |
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2. |
Clock Tree Buffering |
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3. |
Clock Tree Building |
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4. |
Clock Tree Observations |
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Chapter 7 |
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1. |
HTree Buffering Observations |
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2. |
HTree Skew Check |
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3. |
HTree Pulse Width Check Regular And Clock Buffer |
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4. |
Inverter Resistance Difference |
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5. |
Inverter Resistance Match Solution |
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6. |
HTree CBUF Pulse Width Check MET |
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7. |
Duty Cycle Latency Power check Intro |
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8. |
Dynamic Short Circuit Power Revisited |
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9. |
Leakage Power Revisit |
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Chapter 8 |
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1. |
Optimization CheckList |
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2. |
Short Circuit current Revisited |
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3. |
Leakage Current Revisited |
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4. |
Clock Tree Optimized |
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5. |
Optimized Clock Tree Power Latency Check |
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Chapter 9 |
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1. |
Clock Tree Uneven Clk End Points Spread |
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2. |
Logical To Physical Connection |
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3. |
Uneven clock Endpoints HTree CheckList |
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4. |
Advanced HTree Million Flops |
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Chapter 10 |
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1. |
Power Aware CTS Intro To Gates |
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2. |
Delay Table Usage 1 |
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3. |
Delay Table Usage 2 |
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4. |
Clock Gating Using AND Gate and Skew Cal |
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5. |
Skew Issue Solution |
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6. |
OR AND simultaneous clock gating technique |
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7. |
NAND gates as clock gating cells |
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8. |
Clock Gating Technique on Real Chip |
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Chapter 11 |
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1. |
Setup timing Analysis Real Clocks |
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2. |
Intro To Data Arrival And Required Time |
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3. |
Setup Timing Degrade by unbalanced Skew |
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4. |
Hold Timing Analysis Real Clocks |
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5. |
Hold Timing Degrade by unbalanced Skew |
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6. |
Summary |
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11.1 |
Mega QUIZ |
