Certified Ethical Hacker (CEH) Cert Guide is a best-of-breed exam study guide. Leading security consultant and certification expert Michael Gregg shares preparation hints and test-taking tips, helping students identify areas of weakness and improve both conceptual knowledge and hands-on skills. Material is presented in a concise manner, focusing on increasing understanding and retention of exam topics.
Students will get a complete test preparation routine organized around proven series elements and techniques. Exam topic lists make referencing easy. Chapter-ending Exam Preparation Tasks help readers drill on key concepts you must know thoroughly. Review questions help them assess knowledge, and a final preparation chapter guides through tools and resources to help them craft their final study plan. Features - • Reflect complexity, cost, resources, and schedules in planning a chip design project
• Perform hierarchical design decomposition, floorplanning, and physical integration, addressing DFT, DFM, and DFY requirements
• Model functionality and behavior, validate designs, and verify formal equivalency
• Apply EDA tools for logic synthesis, placement, and routing
• Analyze timing, noise, power, and electrical issues
• Prepare for manufacturing release and bring-up, from mastering ECOs to qualification Contents - Preface
TOPIC I: OVERVIEW OF VLSI DESIGN METHODOLOGY
Chapter 1 Introduction
Chapter 2 VLSI Design Methodology
Chapter 3 Hierarchical Design Decomposition
TOPIC II: MODELING
Chapter 4 Cell and IP Modeling
TOPIC III: DESIGN VALIDATION
Chapter 5 Characteristics of Functional Validation
Chapter 6 Characteristics of Formal Equivalency Verification
TOPIC IV: DESIGN IMPLEMENTATION
Chapter 7 Logic Synthesis
Chapter 8 Placement
Chapter 9 Routing
TOPIC V: ELECTRICAL ANALYSIS
Chapter 10 Layout Parasitic Extraction and Electrical Modeling
Chapter 11 Timing Analysis
Chapter 12 Noise Analysis
Chapter 13 Power Analysis
Chapter 14 Power Rail Voltage Drop Analysis
Chapter 15 Electromigration (EM) Reliability Analysis
Chapter 16 Miscellaneous Electrical Analysis Requirements
TOPIC VI: PREPARATION FOR MANUFACTURING RELEASE AND BRING-UP
Chapter 17 ECOs
Chapter 18 Physical Design Verification
Chapter 19 Design for Testability Analysis
Chapter 20 Preparation for Tapeout
Chapter 21 Post-Silicon Debug and Characterization (“Bring-up”) and Product Qualification Epilogue
Index About the author - Thomas Dillinger has more than 30 years of experience in the microelectronics industry, including semiconductor circuit design, fabrication process research, and EDA tool development. He has been responsible for the design methodology development for ASIC, SoC, and complex microprocessor chips for IBM, Sun Microsystems/Oracle, and AMD. He is the author of the book VLSI Engineering and has written for SemiWiki.
Loading...
